OpenAI puts its Jalapeno accelerator design cycle on record with IEEE Spectrum

Sources: IEEE Spectrum report, HN discussion
Summary: Richard Ho, vice president of hardware, and Chris Leary, member of technical staff, describe nine months from first RTL to tape-out and a front-end workflow built on XLS, the open-source high-level synthesis toolchain from Google, chosen because DSLX and C++ look enough like software for models to work on them, with Verilog generated by XLS and Broadcom handling physical design from the gates onward. At Hot Chips 2026 the team reported a 10 percent area reduction on the matrix multiplication units against an optimized human baseline, and after first silicon returned in May internal models raised a DeepSeek multi-head latent attention kernel from 0.31 to 88.94 percent of the chip's theoretical ceiling in roughly 40 hours. Ho states some models used were internal and fine-tuned for chip design and that he does not consider chip design fully automatable, and every performance and schedule figure here is OpenAI's own and is not reproduced independently. The article was published 2026-09-14 and last modified 2026-09-18, so it predates this page.
Why it matters: The reusable part of the account is the toolchain choice, since the models worked on DSLX and C++ with Verilog generated beneath them rather than on Verilog directly.