Dmitry Grinberg argues RISC-V optionality and compressed encodings fail both ends of the market

Sources: Dmitry Grinberg, HN discussion
Summary: The post argues that the extension model and the compressed encodings serve neither embedded nor high-end targets. Its concrete claims are checkable against the specification: a counted 44-cycle interrupt prologue against the Cortex-M0's 27, compressed store-byte offsets limited to zero through three, misa being an optional register that reports optional features and may read as zero, and Zba ratified two years after the base specification.
Why it matters: Optionality that reaches the ISA-identification register itself is what makes portable RISC-V binaries hard to ship.